• Senior Design Verification Engineer

    Microsoft CorporationRedmond, WA 98073

    Job #2707573347

  • The Artificial Intelligence Silicon Engineering team is responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner.

    We are seeking a Senior Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate should be a highly motivated self-starter who will thrive in this cutting-edge technical environment. You will be part of the design verification team, driving many facets of high performance, high bandwidth designs.

    Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

    Responsibilities

    • Define verification strategy, requirements, test environments for IP level verification.

    • Create testplans and write tests to provide complete features coverage.

    • Own verification for complex IPs, including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.

    • Develop and implement technical solutions to complex quality and design challenges.

    • Write scoreboards, sequences, constraints, assertions and functional coverage.

    • Write makefiles and scripts for verification infrastructure.

    • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.

    • Lead small teams of verification engineers and mentor engineers.

    • Collaborate with teams across sites and geographies.

    Other

    • Embody ourCulture (~~~) & Values (~~~)

    Qualifications

    Required/Minimum Qualifications

    • 7+ years of related technical engineering experience

    • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

    • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

    • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

    Additional or Preferred Qualifications

    • 11+ years technical engineering experience

    • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience

    • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience

    • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.

    • 10+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental

    • Experience in test plan development to define test cases, checkers, assertions, and functional coverage points.

    • Experience in verification of many designs at unit level.

    • Knowledge of verification principles, testbenches, UVM, and coverage.

    • Knowledge of system verilog class, constraints, coverage and assertions.

    • Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.

    • Proficient in reading, debugging, and/or designing using Verilog languages

    Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

    Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: ~~~

    Microsoft will accept applications for the role until July 3rd, 2024.

    Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (~~~) .